学术讲座 

演讲者：陈毅坚博士（美国UC-Berkeley博士）

时  间：2010年10月25日  15:30-16:10pm

地  点：北大深研院C203教室

题  目：Semiconductor scaling: continuing challenges into deep nano era 

摘要: 

This presentation will cover the latest progress made in the semiconductor scaling, and discuss some cutting-edge research projects aimed at continuing Moore’s Law into deep nanoscale.  

Starting from EUV (wavelength: 13.5nm) lithography, we shall show this most promising next-generation patterning technology still faces non-trivial technical and cost challenges in mask defect control, defect inspection and resist line edge roughness. On the other hand, maskless lithography has made rapid strides, from an academic idea at early time to currently being well recognized as the main lithographic candidate besides EUV. As a logical combination, maskless EUV lithography using programmable sub-micron MEMS micromirror array is one alternative approach especially attractive for low-volume IC applications wherein EUV masks are simply unaffordable. Research results of design and fabrication of different types of MEMS micromirrors (e.g., vertical comb drive) with nanoscale actuation gaps for maskless EUV lithography will be presented.  

To break the limit of optical lithography, several self-aligned multiple patterning (SAMP) technologies are being used in NAND flash manufacturing to pattern (half-pitch) 25-10nm features. Due to more complex 2-D layouts and slower scaling pace, DRAM and logic devices are still being patterned by 193nm immersion lithography (single exposure). However, strong interest in using SAMP to continue DRAM and logic scaling has started to drive IC design from random 2-D patterns to 1-D gridded grating-type design. Some SAMP (e.g., self-aligned triple patterning) technology can enable more flexible design and require less masks for critical-layer patterning, while its unique lithographic characteristics and the impact on device/circuit functionality are still unexplored topics that are great opportunities for the academic society of IC design.

As part of the global effort to search future transistor structures for memory and logic applications, several non-conventional MOSFET devices will be briefly introduced. Some devices are still in their infancy requiring more demonstration work, and several critical research directions will be identified and discussed.